Xilinx / Vitis_Model_Composer

Vitis Model Composer Examples and Tutorials

Xilinx
Xilinx
Date Created 2020-10-12 (4 years ago)
Commits 2,135 (last one 5 days ago)
Stargazers 75 (0 this week)
Watchers 13 (0 this week)
Forks 29
License unknown
Ranking

RepositoryStats indexes 586,254 repositories, of these Xilinx/Vitis_Model_Composer is ranked #353,415 (40th percentile) for total stargazers, and #165,778 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #19,803/31,352.

Xilinx/Vitis_Model_Composer is also tagged with popular topics, for these it's ranked: fpga (#313/479),  hls (#191/250)

Other Information

Xilinx/Vitis_Model_Composer has 2 open pull requests on Github, 47 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 2 open issues and 4 closed issues.

All Topics
hls acap fpga vitis aiengine

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Github watchers over time, collection started in '23

Recent Commit History

1,686 commits on the default branch (2024.2) since jan '22

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The primary language is C++ but there's also others...

updated: 2024-11-22 @ 06:07pm, id: 303425051 / R_kgDOEhXmGw