Xilinx / Vitis_Model_Composer

Vitis Model Composer Examples and Tutorials

Xilinx
Xilinx
Date Created 2020-10-12 (4 years ago)
Commits 2,170 (last one 23 days ago)
Stargazers 80 (0 this week)
Watchers 13 (0 this week)
Forks 30
License unknown
Ranking

RepositoryStats indexes 599,932 repositories, of these Xilinx/Vitis_Model_Composer is ranked #343,893 (43rd percentile) for total stargazers, and #167,183 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #19,323/32,069.

Xilinx/Vitis_Model_Composer is also tagged with popular topics, for these it's ranked: fpga (#303/489),  hls (#190/253)

Other Information

Xilinx/Vitis_Model_Composer has Github issues enabled, there are 2 open issues and 4 closed issues.

All Topics
hls acap fpga vitis aiengine

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Recent Commit History

1,721 commits on the default branch (2024.2) since jan '22

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The primary language is C++ but there's also others...

updated: 2024-12-21 @ 10:52pm, id: 303425051 / R_kgDOEhXmGw