PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Date Created 2015-06-21 (9 years ago)

Commits 1,990 (last one about a year ago)

Stargazers 306 (0 this week)

Watchers 35 (0 this week)

Forks 58

License apache-2.0

Ranking

RepositoryStats indexes 579,238 repositories, of these PyHDI/veriloggen is ranked #130,314 (78th percentile) for total stargazers, and #61,704 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #22,309/115,001.

PyHDI/veriloggen is also tagged with popular topics, for these it's ranked: python (#6,465/21862), compiler (#383/1045), hardware (#119/442)

Other Information

PyHDI/veriloggen has 1 open pull request on Github, 11 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 22 open issues and 27 closed issues.

There have been 76 releases, the latest one was published on 2023-09-12 (about a year ago) with the name 2.3.0.

All Topics

python compiler hardware pyverilog verilog-hdl high-level-synthesis hardware-construction-language

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

206 commits on the default branch (develop) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-09-29 @ 12:51pm, id: 37813184 / R_kgDOAkD7wA