rhysd / riscv32-cpu-chisel

Learning how to make RISC-V 32bit CPU with Chisel

rhysd
rhysd
Date Created 2021-08-22 (3 years ago)
Commits 67 (last one 3 years ago)
Stargazers 65 (0 this week)
Watchers 4 (0 this week)
Forks 4
License mit
Ranking

RepositoryStats indexes 637,085 repositories, of these rhysd/riscv32-cpu-chisel is ranked #413,766 (35th percentile) for total stargazers, and #367,636 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #1,514/2,042.

rhysd/riscv32-cpu-chisel is also tagged with popular topics, for these it's ranked: cpu (#230/298),  risc-v (#188/283)

Other Information

rhysd/riscv32-cpu-chisel has Github issues enabled, there is 1 open issue and 1 closed issue.

All Topics
cpu chisel risc-v chisel3

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

0 commits on the default branch (main) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
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Languages

The primary language is Scala but there's also others...

ScalaScalaCCMakefileMakefileDockerfileDockerfileAssemblyAssemblyRustRust

updated: 2025-03-31 @ 05:00pm, id: 398720537 / R_kgDOF8P-GQ