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Chisel: A Modern Hardware Design Language
Created
2015-04-27
6,247 commits to main branch, last one 2 days ago
An exquisite superscalar RV32GC processor.
Created
2023-12-24
61 commits to main branch, last one 7 months ago
Provides dot visualizations of chisel/firrtl circuits
Created
2018-10-31
115 commits to master branch, last one 2 years ago
:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl si...
Created
2021-04-30
262 commits to main branch, last one 2 years ago
Yet another toy CPU.
Created
2021-12-14
248 commits to main branch, last one about a year ago
Lectures for the Agile Hardware Design course in Jupyter Notebooks
Created
2021-03-30
221 commits to main branch, last one 9 months ago
Learning how to make RISC-V 32bit CPU with Chisel
Created
2021-08-22
67 commits to main branch, last one 3 years ago
Documentation for YatCPU
Created
2021-12-20
186 commits to master branch, last one about a year ago
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Created
2020-04-08
740 commits to master branch, last one 3 years ago
A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywav...
Created
2024-02-21
113 commits to main branch, last one 2 months ago