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panda5mt
KyogenRV panda5mt
5
44
apache-2.0
3
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
fpga intel riscv rv32i altera chisel risc-v chisel3 avalon-mm
Created 2020-04-08
740 commits to master branch, last one 3 years ago