4 results found Sort:

615
4.2k
apache-2.0
153
Chisel: A Modern Hardware Design Language
Created 2015-04-27
6,335 commits to main branch, last one 13 hours ago
178
737
apache-2.0
60
Flexible Intermediate Representation for RTL
This repository has been archived (exclude archived)
Created 2015-02-13
2,394 commits to 1.6.x branch, last one 6 months ago
13
151
other
9
high-performance RTL simulator
Created 2019-10-17
891 commits to master branch, last one 10 months ago
20
120
apache-2.0
18
Provides dot visualizations of chisel/firrtl circuits
Created 2018-10-31
115 commits to master branch, last one 3 years ago