4 results found Sort:
Chisel: A Modern Hardware Design Language
Created
2015-04-27
6,151 commits to main branch, last one 5 days ago
Flexible Intermediate Representation for RTL
This repository has been archived
(exclude archived)
Created
2015-02-13
2,394 commits to 1.6.x branch, last one 2 months ago
high-performance RTL simulator
Created
2019-10-17
891 commits to master branch, last one 7 months ago
Provides dot visualizations of chisel/firrtl circuits
Created
2018-10-31
115 commits to master branch, last one 2 years ago