4 results found Sort:

chipsalliance
chisel chipsalliance
599
4.0k
apache-2.0
150
Chisel: A Modern Hardware Design Language
rtl scala chisel firrtl chisel3 verilog chip-generator
Created 2015-04-27
6,172 commits to main branch, last one 20 hours ago
chipsalliance
firrtl chipsalliance
177
731
apache-2.0
61
Flexible Intermediate Representation for RTL
firrtl compiler hardware intermediate representation transformation
This repository has been archived (exclude archived)
Created 2015-02-13
2,394 commits to 1.6.x branch, last one 3 months ago
ucsc-vama
essent ucsc-vama
13
140
other
8
high-performance RTL simulator
rtl scala chisel firrtl
Created 2019-10-17
891 commits to master branch, last one 7 months ago
freechipsproject
diagrammer freechipsproject
20
115
apache-2.0
17
Provides dot visualizations of chisel/firrtl circuits
chisel firrtl chisel3 visualization
Created 2018-10-31
115 commits to master branch, last one 2 years ago