chipsalliance / firrtl

Flexible Intermediate Representation for RTL

Date Created 2015-02-13 (9 years ago)

Commits 2,394 (last one 5 months ago)

Stargazers 736 (0 this week)

Watchers 60 (0 this week)

Forks 177

License apache-2.0

This repository has been archived on Github

Ranking

RepositoryStats indexes 609,425 repositories, of these chipsalliance/firrtl is ranked #69,144 (89th percentile) for total stargazers, and #33,663 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #245/2,010.

chipsalliance/firrtl is also tagged with popular topics, for these it's ranked: compiler (#250/1074), hardware (#69/464)

Other Information

chipsalliance/firrtl has 111 open pull requests on Github, 1,546 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 176 open issues and 484 closed issues.

There have been 40 releases, the latest one was published on 2023-01-12 (2 years ago) with the name FIRRTL v1.5.6.

Homepage URL: https://www.chisel-lang.org/firrtl/

All Topics

firrtl compiler hardware intermediate representation transformation

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Github watchers over time, collection started in '23

Recent Commit History

72 commits on the default branch (1.6.x) since jan '22

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Languages

The primary language is Scala but there's also others...

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updated: 2025-01-29 @ 04:42pm, id: 30780129 / R_kgDOAdWq4Q