chipsalliance / chisel

Chisel: A Modern Hardware Design Language

Date Created 2015-04-27 (9 years ago)

Commits 6,151 (last one 5 days ago)

Stargazers 3,977 (3 this week)

Watchers 150 (0 this week)

Forks 597

License apache-2.0

Ranking

RepositoryStats indexes 579,238 repositories, of these chipsalliance/chisel is ranked #12,106 (98th percentile) for total stargazers, and #10,380 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #35/1,982.

chipsalliance/chisel is also tagged with popular topics, for these it's ranked: scala (#32/981), verilog (#3/279)

Other Information

chipsalliance/chisel has 169 open pull requests on Github, 2,755 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 313 open issues and 745 closed issues.

There have been 86 releases, the latest one was published on 2024-07-15 (3 months ago) with the name Chisel v6.5.0.

Homepage URL: https://www.chisel-lang.org/

All Topics

rtl scala chisel firrtl chisel3 verilog chip-generator

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Recent Commit History

1,603 commits on the default branch (main) since jan '22

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Languages

The primary language is Scala but there's also others...

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updated: 2024-11-06 @ 10:43pm, id: 34695562 / R_kgDOAhFpig