chipsalliance / chisel

Chisel: A Modern Hardware Design Language

Date Created 2015-04-27 (9 years ago)

Commits 6,225 (last one a day ago)

Stargazers 4,047 (10 this week)

Watchers 153 (0 this week)

Forks 606

License apache-2.0

Ranking

RepositoryStats indexes 595,890 repositories, of these chipsalliance/chisel is ranked #12,094 (98th percentile) for total stargazers, and #10,185 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #35/1,999.

chipsalliance/chisel is also tagged with popular topics, for these it's ranked: scala (#32/987), verilog (#3/289)

Other Information

chipsalliance/chisel has 160 open pull requests on Github, 2,825 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 316 open issues and 747 closed issues.

There have been 87 releases, the latest one was published on 2024-11-26 (24 days ago) with the name Chisel v6.6.0.

Homepage URL: https://www.chisel-lang.org/

All Topics

rtl scala chisel firrtl chisel3 verilog chip-generator

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Recent Commit History

1,677 commits on the default branch (main) since jan '22

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Languages

The primary language is Scala but there's also others...

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updated: 2024-12-21 @ 03:58pm, id: 34695562 / R_kgDOAhFpig