chipsalliance / chisel

Chisel: A Modern Hardware Design Language

Date Created 2015-04-27 (9 years ago)

Commits 6,172 (last one 19 hours ago)

Stargazers 4,001 (9 this week)

Watchers 150 (0 this week)

Forks 599

License apache-2.0

Ranking

RepositoryStats indexes 584,353 repositories, of these chipsalliance/chisel is ranked #12,094 (98th percentile) for total stargazers, and #10,385 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #35/1,987.

chipsalliance/chisel is also tagged with popular topics, for these it's ranked: scala (#32/983), verilog (#3/282)

Other Information

chipsalliance/chisel has 169 open pull requests on Github, 2,775 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 314 open issues and 745 closed issues.

There have been 86 releases, the latest one was published on 2024-07-15 (4 months ago) with the name Chisel v6.5.0.

Homepage URL: https://www.chisel-lang.org/

All Topics

rtl scala chisel firrtl chisel3 verilog chip-generator

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

1,624 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is Scala but there's also others...

Opengraph Image

updated: 2024-11-20 @ 06:36pm, id: 34695562 / R_kgDOAhFpig