maltanar / fpga-tidbits

Chisel components for FPGA projects

Date Created 2015-06-25 (9 years ago)

Commits 601 (last one about a year ago)

Stargazers 114 (0 this week)

Watchers 10 (0 this week)

Forks 27

License bsd-2-clause

Ranking

RepositoryStats indexes 566,921 repositories, of these maltanar/fpga-tidbits is ranked #260,061 (54th percentile) for total stargazers, and #203,969 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #195/506.

maltanar/fpga-tidbits is also tagged with popular topics, for these it's ranked: fpga (#217/462)

Other Information

maltanar/fpga-tidbits has Github issues enabled, there is 1 open issue and 1 closed issue.

All Topics

fpga chisel hardware-libraries

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

53 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-09-10 @ 03:13am, id: 38038939 / R_kgDOAkRtmw