maltanar / fpga-tidbits

Chisel components for FPGA projects

maltanar
maltanar
Date Created 2015-06-25 (9 years ago)
Commits 601 (last one about a year ago)
Stargazers 122 (0 this week)
Watchers 9 (0 this week)
Forks 27
License bsd-2-clause
Ranking

RepositoryStats indexes 636,587 repositories, of these maltanar/fpga-tidbits is ranked #268,956 (58th percentile) for total stargazers, and #218,450 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #214/628.

maltanar/fpga-tidbits is also tagged with popular topics, for these it's ranked: fpga (#235/523)

Other Information

maltanar/fpga-tidbits has Github issues enabled, there is 1 open issue and 1 closed issue.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

53 commits on the default branch (master) since jan '22

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Issue History

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Languages

The primary language is Verilog but there's also others...

VerilogVerilogScalaScalaC++C++TclTclMakefileMakefileShellShellCC

updated: 2025-03-23 @ 05:52pm, id: 38038939 / R_kgDOAkRtmw