carlosedp / chiselv

A RISC-V Core (RV32I) written in Chisel HDL

Date Created 2021-09-27 (3 years ago)

Commits 318 (last one 6 months ago)

Stargazers 98 (0 this week)

Watchers 6 (0 this week)

Forks 17

License mit

Ranking

RepositoryStats indexes 595,856 repositories, of these carlosedp/chiselv is ranked #298,348 (50th percentile) for total stargazers, and #300,666 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #1,143/1,999.

carlosedp/chiselv is also tagged with popular topics, for these it's ranked: fpga (#264/488), risc-v (#138/268), riscv (#99/167), core (#61/118)

Other Information

carlosedp/chiselv has 1 open pull request on Github, 60 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 3 open issues and 2 closed issues.

All Topics

core fpga riscv chisel risc-v

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

200 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is Scala but there's also others...

updated: 2024-12-20 @ 05:08am, id: 411039788 / R_kgDOGH_4LA