OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor

Date Created 2020-06-13 (3 years ago)

Commits 9,226 (last one 17 hours ago)

Stargazers 4,387 (15 this week)

Watchers 92 (-1 this week)

Forks 608

License other

Ranking

RepositoryStats indexes 523,840 repositories, of these OpenXiangShan/XiangShan is ranked #10,139 (98th percentile) for total stargazers, and #19,723 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #31/1,917.

OpenXiangShan/XiangShan is also tagged with popular topics, for these it's ranked: risc-v (#6/221)

Other Information

OpenXiangShan/XiangShan has 23 open pull requests on Github, 2,233 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 38 open issues and 307 closed issues.

All Topics

chisel risc-v microarchitecture

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

2,483 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Scala but there's also others...

updated: 2024-05-31 @ 09:52pm, id: 271929004 / R_kgDOEDVOrA