MaxXSoft / Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

MaxXSoft
MaxXSoft
Date Created 2020-01-21 (4 years ago)
Commits 325 (last one 3 years ago)
Stargazers 162 (0 this week)
Watchers 5 (0 this week)
Forks 22
License gpl-3.0
Ranking

RepositoryStats indexes 584,353 repositories, of these MaxXSoft/Fuxi is ranked #207,757 (64th percentile) for total stargazers, and #332,313 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #134/535.

MaxXSoft/Fuxi is also tagged with popular topics, for these it's ranked: scala (#465/983),  fpga (#168/478),  cpu (#132/284),  riscv (#75/166)

All Topics
cpu fpga riscv scala chisel

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0 commits on the default branch (master) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-11-16 @ 12:29am, id: 235326677 / R_kgDODgbM1Q