RoaLogic / ahb3lite_interconnect

AHB3-Lite Interconnect

RoaLogic
RoaLogic
Date Created 2017-03-29 (7 years ago)
Commits 145 (last one 10 months ago)
Stargazers 86 (0 this week)
Watchers 9 (0 this week)
Forks 27
License other
Ranking

RepositoryStats indexes 632,894 repositories, of these RoaLogic/ahb3lite_interconnect is ranked #339,497 (46th percentile) for total stargazers, and #217,668 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #95/195.

Other Information

RoaLogic/ahb3lite_interconnect has Github issues enabled, there is 1 open issue and 3 closed issues.

There have been 4 releases, the latest one was published on 2020-11-18 (4 years ago) with the name AHB-Lite Multilayer Interconnect Switch w/ 'ERROR_ON_NO_SLAVE' Detection.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

15 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
443.53.5332.52.5221.51.5110.50.500202020202021202120222022202320232024202420252025

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogTclTclMakefileMakefileFortranFortran

updated: 2025-03-19 @ 03:21pm, id: 86560235 / R_kgDOBSjN6w