10 results found Sort:

lsils
lstools-showcase lsils
31
184
mit
15
Showcase examples for EPFL logic synthesis libraries
examples logic-synthesis
Created 2018-03-06
116 commits to master branch, last one 7 months ago
NYU-MLDA
OpenABC NYU-MLDA
19
115
bsd-3-clause
1
OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
datasets bulls-eye openabc-d benchmarks deep-learning logic-synthesis circuit-benchmarks electronics-design boolean-optimization graph-neural-networks graph-machine-learning logic-synthesis-benchmarks electronics-design-automation
Created 2021-08-24
74 commits to master branch, last one 3 months ago
scale-lab
DRiLLS scale-lab
33
103
bsd-3-clause
10
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
abc aspdac drills deep-learning logic-synthesis machine-learning reinforcement-learning
Created 2018-11-23
84 commits to master branch, last one 3 years ago
lnis-uofu
LSOracle lnis-uofu
41
98
mit
15
IDEA project source files
logic-synthesis
Created 2018-06-14
358 commits to master branch, last one 2 years ago
bojackchen
digital-flow bojackchen
26
73
unknown
4
This is a tutorial on standard digital design flow
synopsys synthesis verilog-hdl logic-synthesis timing-analysis
Created 2018-05-12
45 commits to master branch, last one 3 years ago
nbulsi
also nbulsi
30
68
mit
5
A logic synthesis tool
logic-synthesis majority-based-boolean-function
Created 2019-02-21
396 commits to master branch, last one 2 years ago
cda-tum
fiction cda-tum
23
64
mit
5
An open-source design automation framework for Field-coupled Nanotechnologies
eda fcn nml qca sidb layout routing clocking placement simulation verification emerging-tech nanocomputing logic-synthesis
Created 2018-10-29
538 commits to main branch, last one 3 days ago
workcraft
workcraft workcraft
142
61
mit
10
Toolset to capture, simulate, synthesize and verify graph models
cad eda fsm stg async circuit petri-nets simulation logic-synthesis formal-verification formal-specification
Created 2016-02-07
4,807 commits to master branch, last one a day ago
msoeken
kitty msoeken
77
51
mit
9
C++ truth table library
algorithms logic-synthesis boolean-function
Created 2017-09-21
446 commits to master branch, last one 7 months ago
scale-lab
OpenPhySyn scale-lab
10
50
bsd-3-clause
5
EDA physical synthesis optimization kit
optimization logic-synthesis physical-design physical-synthesis
Created 2019-10-23
391 commits to master branch, last one about a year ago