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lstools-showcase lsils

31

192

mit

14

Showcase examples for EPFL logic synthesis libraries

examples logic-synthesis

Created 2018-03-06

116 commits to master branch, last one 11 months ago

OpenABC NYU-MLDA

21

124

bsd-3-clause

1

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

datasets bulls-eye openabc-d benchmarks deep-learning logic-synthesis circuit-benchmarks electronics-design boolean-optimization graph-neural-networks graph-machine-learning logic-synthesis-benchmarks electronics-design-automation

Created 2021-08-24

74 commits to master branch, last one 7 months ago

DRiLLS scale-lab

36

111

bsd-3-clause

9

DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

abc aspdac drills deep-learning logic-synthesis machine-learning reinforcement-learning

Created 2018-11-23

84 commits to master branch, last one 3 years ago

LSOracle lnis-uofu

41

104

mit

14

IDEA project source files

logic-synthesis

Created 2018-06-14

358 commits to master branch, last one 2 years ago

digital-flow bojackchen

30

75

unknown

3

This is a tutorial on standard digital design flow

synopsys synthesis verilog-hdl logic-synthesis timing-analysis

Created 2018-05-12

45 commits to master branch, last one 3 years ago

also nbulsi

30

72

mit

5

A logic synthesis tool

logic-synthesis majority-based-boolean-function

Created 2019-02-21

396 commits to master branch, last one 2 years ago

fiction cda-tum

25

68

mit

4

An open-source design automation framework for Field-coupled Nanotechnologies

eda fcn nml qca sidb layout routing clocking placement simulation verification emerging-tech nanocomputing logic-synthesis

Created 2018-10-29

687 commits to main branch, last one 2 days ago

workcraft workcraft

142

64

mit

8

Toolset to capture, simulate, synthesize and verify graph models

cad eda fsm stg async circuit petri-nets simulation logic-synthesis formal-verification formal-specification

Created 2016-02-07

4,854 commits to master branch, last one a day ago

kitty msoeken

79

52

mit

8

C++ truth table library

algorithms logic-synthesis boolean-function

Created 2017-09-21

446 commits to master branch, last one about a year ago

OpenPhySyn scale-lab

11

50

bsd-3-clause

4

EDA physical synthesis optimization kit

optimization logic-synthesis physical-design physical-synthesis

Created 2019-10-23

391 commits to master branch, last one about a year ago

HOGA cornell-zhang

4

26

bsd-3-clause

7

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

graph-learning logic-synthesis graph-transformer distributed-training electronic-design-automation

Created 2024-03-06

17 commits to master branch, last one 7 months ago