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bojackchen
digital-flow bojackchen
26
72
unknown
4
This is a tutorial on standard digital design flow
synopsys synthesis verilog-hdl logic-synthesis timing-analysis
Created 2018-05-12
45 commits to master branch, last one 3 years ago
foss-for-synopsys-dwc-arc-processors
embarc_osp foss-for-synopsys-dwc-arc-processors
62
70
bsd-3-clause
46
embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC
arc iot synopsys processors iot-platform iot-framework internet-of-things
Created 2017-03-07
725 commits to master branch, last one about a year ago