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25

120

apache-2.0

8

A complete open-source design-for-testing (DFT) Solution

dft eda atpg jtag testing verilog stuck-at vlsi-cad scan-chains verilog-hdl fault-simulation

Created 2019-06-08

205 commits to main branch, last one 4 days ago

9

73

mit

2

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

cli cpp eda lex atpg vlsi yacc fan-out verilog stuck-at test-pattern vlsi-testing fault-simulation sequential-circuits combinational-circuits electronic-design-automation

Created 2022-10-02

130 commits to main branch, last one 7 months ago

34

71

unknown

9

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

atpg vlsi verilog atalanta

Created 2013-04-30

2 commits to master branch, last one about a month ago