antonblanchard / vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Date Created 2022-05-29 (2 years ago)

Commits 30 (last one 9 months ago)

Stargazers 103 (0 this week)

Watchers 7 (0 this week)

Forks 9

License apache-2.0

Ranking

RepositoryStats indexes 534,551 repositories, of these antonblanchard/vlsiffra is ranked #267,127 (50th percentile) for total stargazers, and #258,950 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #48,114/103,470.

antonblanchard/vlsiffra is also tagged with popular topics, for these it's ranked: verilog (#134/257)

Other Information

antonblanchard/vlsiffra has 3 open pull requests on Github, 12 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 14 open issues and 2 closed issues.

All Topics

vlsi adder booth dadda verilog multiplier amaranth-hdl physical-design

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Github watchers over time, collection started in '23

Recent Commit History

30 commits on the default branch (main) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-06-14 @ 02:13am, id: 497489874 / R_kgDOHacX0g