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641

5.0k

gpl-3.0

68

Digital logic design tool and simulator

fpga vhdl logic circuit logisim verilog circuits education simulator digital-logic timing-diagram digital-circuit digital-circuits logisim-evolution digital-logic-design

Created 2014-09-19

5,059 commits to main branch, last one 3 days ago

kaze yupferris

9

194

apache-2.0

14

An HDL embedded in Rust.

hdl rust digital-logic-design

This repository has been archived (exclude archived)

Created 2019-12-22

217 commits to master branch, last one about a year ago

30-days-of-verilog Akashtailor-exe

4

29

unknown

1

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

vlsi verilog rtl-coding rtl-design 30daysofcode digitalcircuit 30-days-of-code verilog-project verilog-programs digital-logic-design

Created 2023-08-30

48 commits to main branch, last one about a year ago