logisim-evolution / logisim-evolution

Digital logic design tool and simulator

Date Created 2014-09-19 (9 years ago)

Commits 4,942 (last one 4 days ago)

Stargazers 4,411 (15 this week)

Watchers 62 (0 this week)

Forks 577

License gpl-3.0

Ranking

RepositoryStats indexes 523,840 repositories, of these logisim-evolution/logisim-evolution is ranked #10,067 (98th percentile) for total stargazers, and #31,763 for total watchers. Github reports the primary language for this repository as Java, for repositories using this language it is ranked #683/26,422.

logisim-evolution/logisim-evolution is also tagged with popular topics, for these it's ranked: education (#37/567), fpga (#3/425), simulator (#5/308), verilog (#1/251)

Other Information

logisim-evolution/logisim-evolution has 22 open pull requests on Github, 879 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 193 open issues and 645 closed issues.

There have been 29 releases, the latest one was published on 2022-10-02 (about a year ago) with the name Version 3.8.0.

All Topics

fpga vhdl logic circuit logisim verilog circuits education simulator digital-logic timing-diagram digital-circuit digital-circuits logisim-evolution digital-logic-design

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

1,131 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is Java but there's also others...

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updated: 2024-05-31 @ 09:21pm, id: 24217298 / R_kgDOAXGG0g