viktor-prutyanov / drec-fpga-intro

Материалы для курсов по проектированию цифровых вычислительных систем

viktor-prutyanov
viktor-prutyanov
Date Created 2019-01-30 (6 years ago)
Commits 136 (last one a day ago)
Stargazers 96 (0 this week)
Watchers 9 (0 this week)
Forks 33
License mit
Ranking

RepositoryStats indexes 638,211 repositories, of these viktor-prutyanov/drec-fpga-intro is ranked #317,330 (50th percentile) for total stargazers, and #218,649 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #258/630.

viktor-prutyanov/drec-fpga-intro is also tagged with popular topics, for these it's ranked: education (#411/693),  fpga (#280/525),  verilog (#171/313),  risc-v (#146/285)

Other Information

Homepage URL: https://viktor-prutyanov.github.io/drec-fpga-intro/

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

78 commits on the default branch (master) since jan '22

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Issue History

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Languages

The primary language is Verilog but there's also others...

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viktor-prutyanov/drec-fpga-intro

updated: 2025-04-12 @ 08:45pm, id: 168395472 / R_kgDOCgmC0A