viktor-prutyanov / drec-fpga-intro

Материалы для курсов "Введение в проектирование на языке Verilog" (2024+), "Введение в FPGA и Verilog" (2018-2019)

Date Created 2019-01-30 (5 years ago)

Commits 61 (last one 2 days ago)

Stargazers 92 (0 this week)

Watchers 10 (0 this week)

Forks 28

License mit

Ranking

RepositoryStats indexes 579,555 repositories, of these viktor-prutyanov/drec-fpga-intro is ranked #305,089 (47th percentile) for total stargazers, and #205,697 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #238/533.

viktor-prutyanov/drec-fpga-intro is also tagged with popular topics, for these it's ranked: education (#390/632), fpga (#266/475), verilog (#161/280), risc-v (#141/261)

Other Information

Homepage URL: https://viktor-prutyanov.github.io/drec-fpga-intro/

All Topics

asic fpga vlsi risc-v verilog education

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Github watchers over time, collection started in '23

Recent Commit History

3 commits on the default branch (master) since jan '22

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The primary language is Verilog but there's also others...

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updated: 2024-11-06 @ 02:31am, id: 168395472 / R_kgDOCgmC0A