viktor-prutyanov / drec-fpga-intro

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Date Created 2019-01-30 (5 years ago)

Commits 59 (last one about a year ago)

Stargazers 87 (0 this week)

Watchers 10 (0 this week)

Forks 28

License gpl-2.0

Ranking

RepositoryStats indexes 523,840 repositories, of these viktor-prutyanov/drec-fpga-intro is ranked #294,407 (44th percentile) for total stargazers, and #198,405 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #228/447.

viktor-prutyanov/drec-fpga-intro is also tagged with popular topics, for these it's ranked: education (#369/567), fpga (#251/425), verilog (#154/251), risc-v (#132/221)

All Topics

fpga risc-v verilog education

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

1 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

Opengraph Image

updated: 2024-05-15 @ 09:45am, id: 168395472 / R_kgDOCgmC0A