viktor-prutyanov / drec-fpga-intro

Материалы для курсов по проектированию цифровых вычислительных систем

Date Created 2019-01-30 (6 years ago)
Commits 97 (last one 2 days ago)
Stargazers 93 (0 this week)
Watchers 10 (0 this week)
Forks 28
License mit
Ranking

RepositoryStats indexes 612,937 repositories, of these viktor-prutyanov/drec-fpga-intro is ranked #315,371 (49th percentile) for total stargazers, and #209,006 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #252/593.

viktor-prutyanov/drec-fpga-intro is also tagged with popular topics, for these it's ranked: education (#408/659),  fpga (#275/498),  verilog (#168/298),  risc-v (#144/270)

Other Information

Star History

Github stargazers over time

10010090908080707060605050404030302020101000202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

11111111101010101010999920232023Feb '23Feb '23Apr '23Apr '23Jun '23Jun '23Aug '23Aug '23Oct '23Oct '23Dec '23Dec '23Feb '24Feb '24Apr '24Apr '24Jun '24Jun '24Aug '24Aug '24Oct '24Oct '24Dec '24Dec '24Feb '25Feb '25

Recent Commit History

39 commits on the default branch (master) since jan '22

4040353530302525202015151010550020232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

606050504040303020201010002019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
1111110.50.5000000Jul '20Jul '2020212021Jul '21Jul '2120222022Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogMakefileMakefileAssemblyAssemblyPythonPythonCC
Opengraph Image
viktor-prutyanov/drec-fpga-intro

updated: 2025-02-09 @ 11:58am, id: 168395472 / R_kgDOCgmC0A