sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Date Created 2015-11-08 (9 years ago)

Commits 1,342 (last one 4 months ago)

Stargazers 649 (0 this week)

Watchers 51 (0 this week)

Forks 107

License apache-2.0

Ranking

RepositoryStats indexes 634,548 repositories, of these sergeykhbr/riscv_vhdl is ranked #77,944 (88th percentile) for total stargazers, and #40,350 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #38/625.

sergeykhbr/riscv_vhdl is also tagged with popular topics, for these it's ranked: qt (#168/801), simulator (#48/351), debugger (#97/342), cpu (#71/298), riscv (#38/181)

Other Information

sergeykhbr/riscv_vhdl has Github issues enabled, there are 3 open issues and 40 closed issues.

Homepage URL: http://sergeykhbr.github.io/riscv_vhdl/

All Topics

qt cpu soc vhdl riscv systemc debugger simulator

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Recent Commit History

339 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2025-04-03 @ 09:58am, id: 45797714 / R_kgDOArrRUg