sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Date Created 2015-11-08 (9 years ago)

Commits 1,342 (last one 8 days ago)

Stargazers 626 (0 this week)

Watchers 53 (0 this week)

Forks 104

License apache-2.0

Ranking

RepositoryStats indexes 585,880 repositories, of these sergeykhbr/riscv_vhdl is ranked #76,382 (87th percentile) for total stargazers, and #38,730 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #36/538.

sergeykhbr/riscv_vhdl is also tagged with popular topics, for these it's ranked: qt (#164/760), simulator (#47/333), debugger (#92/325), cpu (#72/284), riscv (#38/166)

Other Information

sergeykhbr/riscv_vhdl has Github issues enabled, there are 2 open issues and 40 closed issues.

Homepage URL: http://sergeykhbr.github.io/riscv_vhdl/

All Topics

qt cpu soc vhdl riscv systemc debugger simulator

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Recent Commit History

339 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-11-23 @ 10:13am, id: 45797714 / R_kgDOArrRUg