sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Date Created 2015-11-08 (8 years ago)

Commits 1,337 (last one 9 months ago)

Stargazers 619 (0 this week)

Watchers 53 (0 this week)

Forks 102

License apache-2.0

Ranking

RepositoryStats indexes 564,918 repositories, of these sergeykhbr/riscv_vhdl is ranked #75,487 (87th percentile) for total stargazers, and #38,495 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #36/504.

sergeykhbr/riscv_vhdl is also tagged with popular topics, for these it's ranked: qt (#165/736), simulator (#48/324), debugger (#91/316), cpu (#72/279), riscv (#36/162)

Other Information

sergeykhbr/riscv_vhdl has Github issues enabled, there are 2 open issues and 39 closed issues.

Homepage URL: http://sergeykhbr.github.io/riscv_vhdl/

All Topics

qt cpu soc vhdl riscv systemc debugger simulator

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Recent Commit History

334 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-09-15 @ 12:14pm, id: 45797714 / R_kgDOArrRUg