Eyantra698Sumanto / Spice-to-Verilog-Converter

Spice to Verilog Converter

Date Created 2022-06-03 (2 years ago)

Commits 11 (last one 2 years ago)

Stargazers 12 (0 this week)

Watchers 1 (0 this week)

Forks 1

License gpl-3.0

Ranking

RepositoryStats indexes 631,351 repositories, of these Eyantra698Sumanto/Spice-to-Verilog-Converter is ranked #630,170 (0th percentile) for total stargazers, and #556,009 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #128,639/128,766.

Eyantra698Sumanto/Spice-to-Verilog-Converter is also tagged with popular topics, for these it's ranked: verilog (#307/307)

Other Information

Eyantra698Sumanto/Spice-to-Verilog-Converter has Github issues enabled, there is 1 open issue and 0 closed issues.

All Topics

spice analog verilog verilog-hdl system-verilog

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

11 commits on the default branch (main) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-12-08 @ 04:44am, id: 499661230 / R_kgDOHcg5rg