DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

DOUDIU
DOUDIU
Date Created 2022-07-28 (2 years ago)
Commits 27 (last one 8 months ago)
Stargazers 32 (0 this week)
Watchers 1 (0 this week)
Forks 0
License unknown
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RepositoryStats indexes 595,856 repositories, of these DOUDIU/Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm is ranked #560,208 (6th percentile) for total stargazers, and #544,643 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #523/563.

DOUDIU/Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm is also tagged with popular topics, for these it's ranked: fpga (#468/488)

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fpga canny vivado modelsim

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27 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-12-17 @ 08:45pm, id: 518800339 / R_kgDOHuxD0w