DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

DOUDIU
DOUDIU
Date Created 2022-07-28 (2 years ago)
Commits 27 (last one 11 months ago)
Stargazers 34 (0 this week)
Watchers 1 (0 this week)
Forks 0
License unknown
Ranking

RepositoryStats indexes 631,351 repositories, of these DOUDIU/Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm is ranked #579,221 (8th percentile) for total stargazers, and #556,009 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #558/617.

DOUDIU/Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm is also tagged with popular topics, for these it's ranked: fpga (#497/515)

All Topics
fpga canny vivado modelsim

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Recent Commit History

27 commits on the default branch (main) since jan '22

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Issue History

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Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogC++C++

updated: 2025-02-23 @ 10:44am, id: 518800339 / R_kgDOHuxD0w