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bsd-3-clause

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design

Created 2018-08-19

343 commits to master branch, last one 9 days ago

275

867

other

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

ip rtl core riscv rv32e rv32i risc-v rv32emc rv32imc verilog

Created 2017-05-09

67 commits to master branch, last one 5 days ago