syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Date Created 2017-05-09 (7 years ago)

Commits 67 (last one 5 days ago)

Stargazers 867 (3 this week)

Watchers 51 (0 this week)

Forks 275

License other

Ranking

RepositoryStats indexes 584,353 repositories, of these syntacore/scr1 is ranked #58,134 (90th percentile) for total stargazers, and #40,481 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #9/173.

syntacore/scr1 is also tagged with popular topics, for these it's ranked: verilog (#30/282), risc-v (#35/263), riscv (#27/166), core (#18/116)

Other Information

syntacore/scr1 has Github issues enabled, there is 1 open issue and 56 closed issues.

All Topics

ip rtl core riscv rv32e rv32i risc-v rv32emc rv32imc verilog

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

7 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-20 @ 03:28pm, id: 90702468 / R_kgDOBWgChA