syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

syntacore
syntacore
Date Created 2017-05-09 (7 years ago)
Commits 67 (last one 4 months ago)
Stargazers 907 (2 this week)
Watchers 52 (0 this week)
Forks 288
License other
Ranking

RepositoryStats indexes 638,211 repositories, of these syntacore/scr1 is ranked #58,629 (91st percentile) for total stargazers, and #39,528 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #10/199.

syntacore/scr1 is also tagged with popular topics, for these it's ranked: verilog (#32/313),  risc-v (#38/285),  riscv (#28/181),  core (#17/124)

Other Information

syntacore/scr1 has 2 open pull requests on Github, 5 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 2 open issues and 56 closed issues.

Star History

Github stargazers over time

1k1k900900800800700700600600500500400400300300200200100100002018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

535352.552.5525251.551.5515150.550.5505049.549.5494920232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

7 commits on the default branch (master) since jan '22

7766554433221100Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

2525202015151010550020172017201820182019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
606050504040303020201010002018201820192019202020202021202120222022202320232024202420252025

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogCCMakefileMakefileAssemblyAssembly

updated: 2025-04-13 @ 10:41am, id: 90702468 / R_kgDOBWgChA