syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Date Created 2017-05-09 (7 years ago)

Commits 65 (last one about a month ago)

Stargazers 804 (0 this week)

Watchers 50 (0 this week)

Forks 267

License other

Ranking

RepositoryStats indexes 533,341 repositories, of these syntacore/scr1 is ranked #59,289 (89th percentile) for total stargazers, and #40,914 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #10/152.

syntacore/scr1 is also tagged with popular topics, for these it's ranked: verilog (#29/256), risc-v (#32/224), riscv (#23/147), core (#18/107)

Other Information

syntacore/scr1 has 2 open pull requests on Github, 5 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 2 open issues and 53 closed issues.

All Topics

ip rtl core riscv rv32e rv32i risc-v rv32emc rv32imc verilog

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

5 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-06-23 @ 06:03pm, id: 90702468 / R_kgDOBWgChA