syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Date Created 2017-05-09 (7 years ago)
Commits 67 (last one 3 months ago)
Stargazers 898 (1 this week)
Watchers 53 (0 this week)
Forks 284
License other
Ranking

RepositoryStats indexes 617,578 repositories, of these syntacore/scr1 is ranked #57,989 (91st percentile) for total stargazers, and #39,093 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #10/192.

syntacore/scr1 is also tagged with popular topics, for these it's ranked: verilog (#31/299),  risc-v (#38/271),  riscv (#28/175),  core (#17/121)

Other Information

syntacore/scr1 has 2 open pull requests on Github, 5 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 2 open issues and 56 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

535352.552.5525251.551.5515150.550.5505049.549.5494920232023Feb '23Feb '23Apr '23Apr '23Jun '23Jun '23Aug '23Aug '23Oct '23Oct '23Dec '23Dec '23Feb '24Feb '24Apr '24Apr '24Jun '24Jun '24Aug '24Aug '24Oct '24Oct '24Dec '24Dec '24Feb '25Feb '25

Recent Commit History

7 commits on the default branch (master) since jan '22

7766554433221100Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogCCMakefileMakefileAssemblyAssembly

updated: 2025-02-18 @ 04:20am, id: 90702468 / R_kgDOBWgChA