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SCR1 is a high-quality open-source RISC-V MCU core in Verilog

ip rtl core riscv rv32e rv32i risc-v rv32emc rv32imc verilog

Created 2017-05-09

67 commits to master branch, last one 4 months ago

150

gpl-3.0

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

cpu rtl asic fpga llvm clang riscv risc-v rv32imc verilog coremark in-order openlane processor teknofest verification pipeline-processor computer-architecture

Created 2022-12-21

532 commits to main branch, last one about a year ago