martinKindall / risc-v-single-cycle

A Single Cycle Risc-V 32 bit CPU

Date Created 2022-12-21 (about a year ago)

Commits 29 (last one about a year ago)

Stargazers 34 (0 this week)

Watchers 4 (0 this week)

Forks 3

License unknown

Ranking

RepositoryStats indexes 584,353 repositories, of these martinKindall/risc-v-single-cycle is ranked #542,506 (7th percentile) for total stargazers, and #373,290 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #158/173.

martinKindall/risc-v-single-cycle is also tagged with popular topics, for these it's ranked: riscv (#158/166)

All Topics

riscv rv32i basys3 riscv32 basys3-fpga systemverilog riscv-assembly single-cycle-processor

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

29 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

No issues have been posted

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-19 @ 08:05am, id: 580967817 / R_kgDOIqDdiQ