darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Date Created 2018-08-19 (6 years ago)
Commits 370 (last one 5 days ago)
Stargazers 2,212 (7 this week)
Watchers 95 (0 this week)
Forks 295
License bsd-3-clause
Ranking

RepositoryStats indexes 618,350 repositories, of these darklife/darkriscv is ranked #23,881 (96th percentile) for total stargazers, and #19,358 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #4/601.

darklife/darkriscv is also tagged with popular topics, for these it's ranked: fpga (#10/503),  verilog (#8/299),  cpu (#31/295),  risc-v (#16/271),  riscv (#11/175),  core (#7/121)

Other Information

darklife/darkriscv has 1 open pull request on Github, 27 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 8 open issues and 32 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

177 commits on the default branch (master) since jan '22

180180160160140140120120100100808060604040202000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogTeXTeXTclTclShellShell

updated: 2025-02-22 @ 06:43am, id: 145329615 / R_kgDOCKmNzw