darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Date Created 2018-08-19 (5 years ago)

Commits 287 (last one 4 days ago)

Stargazers 1,942 (8 this week)

Watchers 87 (0 this week)

Forks 274

License bsd-3-clause

Ranking

RepositoryStats indexes 534,551 repositories, of these darklife/darkriscv is ranked #25,064 (95th percentile) for total stargazers, and #21,189 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #4/459.

darklife/darkriscv is also tagged with popular topics, for these it's ranked: fpga (#11/435), verilog (#9/257), risc-v (#14/225), riscv (#9/147), core (#8/107)

Other Information

darklife/darkriscv has 1 open pull request on Github, 20 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 8 open issues and 32 closed issues.

All Topics

cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

94 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-06-28 @ 10:14am, id: 145329615 / R_kgDOCKmNzw