darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Date Created 2018-08-19 (6 years ago)

Commits 341 (last one 27 days ago)

Stargazers 2,112 (-2 this week)

Watchers 94 (0 this week)

Forks 285

License bsd-3-clause

Ranking

RepositoryStats indexes 579,238 repositories, of these darklife/darkriscv is ranked #24,014 (96th percentile) for total stargazers, and #19,422 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #4/533.

darklife/darkriscv is also tagged with popular topics, for these it's ranked: fpga (#10/474), cpu (#31/284), verilog (#8/279), risc-v (#15/261), riscv (#10/165), core (#7/115)

Other Information

darklife/darkriscv has 1 open pull request on Github, 20 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 8 open issues and 32 closed issues.

All Topics

cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

148 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-05 @ 10:20pm, id: 145329615 / R_kgDOCKmNzw