FelipeFFerreira / ITA-CORES

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

Date Created 2023-06-13 (about a year ago)

Commits 121 (last one about a year ago)

Stargazers 40 (0 this week)

Watchers 2 (0 this week)

Forks 3

License other

Ranking

RepositoryStats indexes 589,134 repositories, of these FelipeFFerreira/ITA-CORES is ranked #515,952 (12th percentile) for total stargazers, and #481,361 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #473/549.

FelipeFFerreira/ITA-CORES is also tagged with popular topics, for these it's ranked: framework (#1,686/1812), risc-v (#236/265)

Other Information

FelipeFFerreira/ITA-CORES has Github issues enabled, there is 1 open issue and 0 closed issues.

All Topics

asic chip rv32i risc-v femtorv32 framework physical-design physical-design-automation

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Recent Commit History

121 commits on the default branch (master) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-10-21 @ 05:53am, id: 653334239 / R_kgDOJvEW3w