ultraembedded / riscv

RISC-V CPU Core (RV32IM)

ultraembedded
ultraembedded
Date Created 2014-08-31 (10 years ago)
Commits 48 (last one 3 years ago)
Stargazers 1,400 (5 this week)
Watchers 53 (0 this week)
Forks 250
License bsd-3-clause
Ranking

RepositoryStats indexes 631,885 repositories, of these ultraembedded/riscv is ranked #38,929 (94th percentile) for total stargazers, and #38,572 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #15/617.

ultraembedded/riscv is also tagged with popular topics, for these it's ranked: fpga (#24/516),  verilog (#20/307),  cpu (#46/297),  risc-v (#28/281)

Other Information

ultraembedded/riscv has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 14 open issues and 4 closed issues.

Star History

Github stargazers over time

1.4k1.4k1.2k1.2k1k1k80080060060040040020020000201720172018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

545452525050484846464444424220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is Verilog but there's also others...

VerilogVerilogC++C++CCMakefileMakefile

updated: 2025-03-26 @ 03:05am, id: 23511343 / R_kgDOAWbBLw