ultraembedded / riscv

RISC-V CPU Core (RV32IM)

Date Created 2014-08-31 (10 years ago)
Commits 48 (last one 3 years ago)
Stargazers 1,353 (4 this week)
Watchers 52 (0 this week)
Forks 247
License bsd-3-clause
Ranking

RepositoryStats indexes 615,809 repositories, of these ultraembedded/riscv is ranked #39,688 (94th percentile) for total stargazers, and #39,935 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #15/600.

ultraembedded/riscv is also tagged with popular topics, for these it's ranked: fpga (#24/502),  verilog (#20/299),  cpu (#47/295),  risc-v (#28/271)

Other Information

ultraembedded/riscv has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 14 open issues and 4 closed issues.

Star History

Github stargazers over time

1.4k1.4k1.2k1.2k1k1k80080060060040040020020000201720172018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

5252515150504949484847474646454544444343424220232023Feb '23Feb '23Apr '23Apr '23Jun '23Jun '23Aug '23Aug '23Oct '23Oct '23Dec '23Dec '23Feb '24Feb '24Apr '24Apr '24Jun '24Jun '24Aug '24Aug '24Oct '24Oct '24Dec '24Dec '24Feb '25Feb '25

Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
181816161414121210108866442200202020202021202120222022202320232024202420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogC++C++CCMakefileMakefile

updated: 2025-02-14 @ 03:28pm, id: 23511343 / R_kgDOAWbBLw