ultraembedded / riscv

RISC-V CPU Core (RV32IM)

Date Created 2014-08-31 (10 years ago)

Commits 48 (last one 3 years ago)

Stargazers 1,301 (5 this week)

Watchers 52 (0 this week)

Forks 238

License bsd-3-clause

Ranking

RepositoryStats indexes 595,890 repositories, of these ultraembedded/riscv is ranked #40,429 (93rd percentile) for total stargazers, and #39,746 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #15/563.

ultraembedded/riscv is also tagged with popular topics, for these it's ranked: fpga (#26/488), verilog (#22/289), cpu (#48/285), risc-v (#28/268)

Other Information

ultraembedded/riscv has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 14 open issues and 4 closed issues.

All Topics

cpu asic fpga rv32i risc-v rv32im verilog verilator riscv-linux verification pipeline-processor

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

0 commits on the default branch (master) since jan '22

No recent commits to this repository

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-12-20 @ 09:13am, id: 23511343 / R_kgDOAWbBLw