ZipCPU / wb2axip

Bus bridges and other odds and ends

Date Created 2016-09-21 (8 years ago)

Commits 481 (last one 9 months ago)

Stargazers 484 (0 this week)

Watchers 31 (0 this week)

Forks 101

License unknown

Ranking

RepositoryStats indexes 579,238 repositories, of these ZipCPU/wb2axip is ranked #92,344 (84th percentile) for total stargazers, and #70,302 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #49/533.

ZipCPU/wb2axip is also tagged with popular topics, for these it's ranked: fpga (#74/474)

Other Information

ZipCPU/wb2axip has 1 open pull request on Github, 3 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 4 open issues and 48 closed issues.

All Topics

fpga gplv3 xilinx axi-bus wishbone wishbone-bus xilinx-vivado

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

30 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-05 @ 04:16pm, id: 68850972 / R_kgDOBBqVHA