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A small, light weight, RISC CPU soft core
Created
2016-09-21
817 commits to master branch, last one 2 months ago
Bus bridges and other odds and ends
Created
2016-09-21
481 commits to master branch, last one 9 months ago
A simple, basic, formally verified UART controller
Created
2016-09-21
160 commits to master branch, last one 9 months ago
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Created
2016-09-21
248 commits to master branch, last one 22 days ago
A utility for Composing FPGA designs from Peripherals
Created
2017-03-29
301 commits to master branch, last one 9 months ago
An Open Source configuration of the Arty platform
Created
2016-09-26
398 commits to master branch, last one 4 years ago
Simple UART controller for FPGA written in VHDL
Created
2015-07-24
62 commits to master branch, last one 3 years ago
A wishbone controlled scope for FPGA's
Created
2016-09-21
50 commits to master branch, last one 9 months ago
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Created
2016-02-20
146 commits to develop branch, last one 4 days ago