ZipCPU / openarty

An Open Source configuration of the Arty platform

Date Created 2016-09-26 (8 years ago)

Commits 398 (last one 4 years ago)

Stargazers 122 (0 this week)

Watchers 15 (0 this week)

Forks 24

License unknown

Ranking

RepositoryStats indexes 595,856 repositories, of these ZipCPU/openarty is ranked #257,167 (57th percentile) for total stargazers, and #146,501 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #191/563.

ZipCPU/openarty is also tagged with popular topics, for these it's ranked: fpga (#218/488)

Other Information

ZipCPU/openarty has Github issues enabled, there is 1 open issue and 3 closed issues.

All Topics

arty fpga zipcpu fpga-soc wishbone verilator wishbone-bus

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0 commits on the default branch (master) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-12-02 @ 06:14pm, id: 69269176 / R_kgDOBCD2uA