Xilinx / SDAccel_Examples

SDAccel Examples

Xilinx
Xilinx
Date Created 2016-08-05 (8 years ago)
Commits 1,731 (last one 4 years ago)
Stargazers 357 (0 this week)
Watchers 75 (0 this week)
Forks 210
License other
Ranking

RepositoryStats indexes 637,312 repositories, of these Xilinx/SDAccel_Examples is ranked #123,149 (81st percentile) for total stargazers, and #25,620 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #6,882/34,001.

Xilinx/SDAccel_Examples is also tagged with popular topics, for these it's ranked: cpp (#1,044/3647),  c (#960/2887),  aws (#618/2618),  fpga (#100/523),  opencl (#60/171)

Other Information

Xilinx/SDAccel_Examples has 1 open pull request on Github, 2 pull requests have been merged over the lifetime of the repository.

Star History

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Watcher History

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Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

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Issue History

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Languages

The primary language is C++ but there's also others...

C++C++MakefileMakefileCCSystemVerilogSystemVerilogVerilogVerilogPythonPythonTclTclObjective-CObjective-CShellShell

updated: 2025-03-12 @ 07:17pm, id: 65037216 / R_kgDOA-BjoA