eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Date Created 2020-02-15 (5 years ago)

Commits 429 (last one 8 days ago)

Stargazers 915 (4 this week)

Watchers 35 (0 this week)

Forks 205

License unknown

Ranking

RepositoryStats indexes 626,055 repositories, of these eugene-tarassov/vivado-risc-v is ranked #57,436 (91st percentile) for total stargazers, and #61,186 for total watchers. Github reports the primary language for this repository as Tcl, for repositories using this language it is ranked #4/137.

eugene-tarassov/vivado-risc-v is also tagged with popular topics, for these it's ranked: linux (#1,143/6162), fpga (#43/507), risc-v (#36/277), riscv (#27/178)

Other Information

eugene-tarassov/vivado-risc-v has Github issues enabled, there are 56 open issues and 165 closed issues.

There have been 6 releases, the latest one was published on 2024-03-26 (11 months ago) with the name Release v3.7.0.

All Topics

boom fpga kc705 linux riscv vc707 risc-v vivado xilinx arty-a7 genesys2 rocketchip nexys-video

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

175 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Tcl but there's also others...

updated: 2025-03-13 @ 05:52pm, id: 240625745 / R_kgDODleoUQ