eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Date Created 2020-02-15 (4 years ago)

Commits 426 (last one 10 days ago)

Stargazers 873 (5 this week)

Watchers 35 (0 this week)

Forks 197

License unknown

Ranking

RepositoryStats indexes 595,856 repositories, of these eugene-tarassov/vivado-risc-v is ranked #58,358 (90th percentile) for total stargazers, and #62,105 for total watchers. Github reports the primary language for this repository as Tcl, for repositories using this language it is ranked #5/130.

eugene-tarassov/vivado-risc-v is also tagged with popular topics, for these it's ranked: linux (#1,151/5945), fpga (#44/488), risc-v (#37/268), riscv (#28/167)

Other Information

eugene-tarassov/vivado-risc-v has Github issues enabled, there are 49 open issues and 163 closed issues.

There have been 6 releases, the latest one was published on 2024-03-26 (9 months ago) with the name Release v3.7.0.

All Topics

boom fpga kc705 linux riscv vc707 risc-v vivado xilinx arty-a7 genesys2 rocketchip nexys-video

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

172 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Tcl but there's also others...

updated: 2024-12-21 @ 01:53pm, id: 240625745 / R_kgDODleoUQ