eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Date Created 2020-02-15 (4 years ago)

Commits 417 (last one 8 days ago)

Stargazers 775 (3 this week)

Watchers 33 (0 this week)

Forks 180

License unknown

Ranking

RepositoryStats indexes 534,880 repositories, of these eugene-tarassov/vivado-risc-v is ranked #61,445 (89th percentile) for total stargazers, and #64,873 for total watchers. Github reports the primary language for this repository as Tcl, for repositories using this language it is ranked #5/127.

eugene-tarassov/vivado-risc-v is also tagged with popular topics, for these it's ranked: linux (#1,174/5385), fpga (#44/435), risc-v (#35/226), riscv (#25/147)

Other Information

eugene-tarassov/vivado-risc-v has Github issues enabled, there are 43 open issues and 153 closed issues.

There have been 6 releases, the latest one was published on 2024-03-26 (3 months ago) with the name Release v3.7.0.

All Topics

boom fpga kc705 linux riscv vc707 risc-v vivado xilinx arty-a7 genesys2 rocketchip nexys-video

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

163 commits on the default branch (master) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Tcl but there's also others...

updated: 2024-07-01 @ 12:28pm, id: 240625745 / R_kgDODleoUQ