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BrianHGinc
BrianHG-DDR3-Controller BrianHGinc
29
67
unknown
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DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
hdl ddr3 fpga intel altera xilinx lattice verilog testbenches systemverilog
Created 2021-08-29
110 commits to main branch, last one about a month ago
snbk001
Verilog-Design-Examples snbk001
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65
unknown
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Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion,...
verilog testbenches verilog-hdl verilog-code self-checking verilog-design verilog-project verilog-programs
Created 2022-01-14
102 commits to main branch, last one about a year ago