snbk001 / Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

Date Created 2022-01-14 (2 years ago)

Commits 102 (last one about a year ago)

Stargazers 90 (1 this week)

Watchers 1 (0 this week)

Forks 15

License unknown

Ranking

RepositoryStats indexes 565,279 repositories, of these snbk001/Verilog-Design-Examples is ranked #304,154 (46th percentile) for total stargazers, and #521,451 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #234/505.

snbk001/Verilog-Design-Examples is also tagged with popular topics, for these it's ranked: verilog (#160/272)

All Topics

verilog testbenches verilog-hdl verilog-code self-checking verilog-design verilog-project verilog-programs

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102 commits on the default branch (main) since jan '22

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The only known language in this repository is Verilog

updated: 2024-09-25 @ 08:59am, id: 447973979 / R_kgDOGrOKWw