ben-marshall / uart

A simple implementation of a UART modem in Verilog.

Date Created 2017-02-04 (8 years ago)
Commits 50 (last one 3 years ago)
Stargazers 123 (0 this week)
Watchers 3 (0 this week)
Forks 22
License mit
Ranking

RepositoryStats indexes 632,894 repositories, of these ben-marshall/uart is ranked #265,953 (58th percentile) for total stargazers, and #417,466 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #210/618.

ben-marshall/uart is also tagged with popular topics, for these it's ranked: fpga (#231/515),  hardware (#235/476),  verilog (#142/308)

Other Information

ben-marshall/uart has Github issues enabled, there are 3 open issues and 2 closed issues.

Homepage URL: https://ben-marshall.github.io/uart/

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
554.54.5443.53.5332.52.5221.51.5110.50.500Jul '21Jul '2120222022Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogMakefileMakefilePythonPythonShellShell

updated: 2025-03-22 @ 11:24am, id: 80923531 / R_kgDOBNLLiw