TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Date Created 2020-05-13 (4 years ago)

Commits 768 (last one a day ago)

Stargazers 562 (1 this week)

Watchers 24 (0 this week)

Forks 45

License gpl-3.0

Ranking

RepositoryStats indexes 579,555 repositories, of these TerosTechnology/vscode-terosHDL is ranked #82,419 (86th percentile) for total stargazers, and #91,916 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #9/176.

TerosTechnology/vscode-terosHDL is also tagged with popular topics, for these it's ranked: fpga (#66/475), verilog (#48/280)

Other Information

TerosTechnology/vscode-terosHDL has 2 open pull requests on Github, 212 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 188 open issues and 279 closed issues.

There have been 24 releases, the latest one was published on 2024-11-05 (a day ago) with the name v6.0.14.

Homepage URL: https://terostechnology.github.io/terosHDLdoc/

All Topics

fpga vhdl verilog systemverilog

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

416 commits on the default branch (dev) since jan '22

Yearly Commits

Commits to the default branch (dev) per year

Issue History

Languages

The primary language is VHDL but there's also others...

updated: 2024-11-06 @ 02:56am, id: 263754522 / R_kgDOD7iTGg