TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Date Created 2020-05-13 (4 years ago)

Commits 679 (last one a day ago)

Stargazers 518 (0 this week)

Watchers 21 (0 this week)

Forks 42

License unknown

Ranking

RepositoryStats indexes 528,822 repositories, of these TerosTechnology/vscode-terosHDL is ranked #83,068 (84th percentile) for total stargazers, and #103,016 for total watchers. Github reports the primary language for this repository as JavaScript, for repositories using this language it is ranked #11,444/61,348.

TerosTechnology/vscode-terosHDL is also tagged with popular topics, for these it's ranked: fpga (#67/429), verilog (#45/254)

Other Information

TerosTechnology/vscode-terosHDL has 2 open pull requests on Github, 184 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 168 open issues and 253 closed issues.

There have been 22 releases, the latest one was published on 2024-06-11 (a day ago) with the name v6.0.1alpha.

Homepage URL: https://terostechnology.github.io/terosHDLdoc/

All Topics

fpga vhdl verilog systemverilog

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

327 commits on the default branch (dev) since jan '22

Yearly Commits

Commits to the default branch (dev) per year

Issue History

Languages

The primary language is JavaScript but there's also others...

updated: 2024-06-11 @ 11:21pm, id: 263754522 / R_kgDOD7iTGg