stnolting / neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Date Created 2022-01-11 (2 years ago)

Commits 507 (last one 2 days ago)

Stargazers 63 (0 this week)

Watchers 8 (0 this week)

Forks 17

License bsd-3-clause

Ranking

RepositoryStats indexes 584,353 repositories, of these stnolting/neorv32-setups is ranked #396,721 (32nd percentile) for total stargazers, and #244,799 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #107/177.

stnolting/neorv32-setups is also tagged with popular topics, for these it's ranked: fpga (#348/478), verilog (#212/282), risc-v (#178/263)

Other Information

stnolting/neorv32-setups has Github issues enabled, there are 2 open issues and 15 closed issues.

Homepage URL: https://github.com/stnolting/neorv32

All Topics

soc fpga ghdl vhdl intel yosys risc-v xilinx lattice neorv32 verilog

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Recent Commit History

507 commits on the default branch (main) since jan '22

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Languages

The primary language is VHDL but there's also others...

updated: 2024-11-19 @ 08:45am, id: 446662760 / R_kgDOGp-IaA