WangXuan95 / FPGA-DDR-SDRAM

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。

Date Created 2021-01-27 (4 years ago)
Commits 19 (last one about a year ago)
Stargazers 170 (0 this week)
Watchers 4 (0 this week)
Forks 35
License gpl-3.0
Ranking

RepositoryStats indexes 631,885 repositories, of these WangXuan95/FPGA-DDR-SDRAM is ranked #211,304 (67th percentile) for total stargazers, and #365,509 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #144/617.

WangXuan95/FPGA-DDR-SDRAM is also tagged with popular topics, for these it's ranked: fpga (#178/516),  verilog (#113/307)

Other Information

WangXuan95/FPGA-DDR-SDRAM has Github issues enabled, there is 1 open issue and 2 closed issues.

Homepage URL: https://gitee.com/wangxuan95/FPGA-DDR-SDRAM

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

15 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
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Closed Issues
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Languages

The primary language is Verilog but there's also others...

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updated: 2025-03-25 @ 01:09am, id: 333377514 / R_kgDOE97v6g