WangXuan95 / FPGA-DDR-SDRAM

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

Date Created 2021-01-27 (4 years ago)

Commits 19 (last one about a year ago)

Stargazers 159 (0 this week)

Watchers 4 (0 this week)

Forks 34

License gpl-3.0

Ranking

RepositoryStats indexes 609,066 repositories, of these WangXuan95/FPGA-DDR-SDRAM is ranked #216,407 (64th percentile) for total stargazers, and #381,252 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #144/588.

WangXuan95/FPGA-DDR-SDRAM is also tagged with popular topics, for these it's ranked: fpga (#182/498), verilog (#115/297)

Other Information

WangXuan95/FPGA-DDR-SDRAM has Github issues enabled, there is 1 open issue and 2 closed issues.

Homepage URL: https://gitee.com/wangxuan95/FPGA-DDR-SDRAM

All Topics

rtl axi4 ddr1 fpga verilog ddr-sdram soft-core controller

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Recent Commit History

15 commits on the default branch (main) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2025-01-18 @ 03:33am, id: 333377514 / R_kgDOE97v6g