ultraembedded / core_dbg_bridge

UART -> AXI Bridge

ultraembedded
ultraembedded
Date Created 2019-08-11 (5 years ago)
Commits 5 (last one 3 years ago)
Stargazers 58 (0 this week)
Watchers 5 (0 this week)
Forks 17
License lgpl-2.1
Ranking

RepositoryStats indexes 586,601 repositories, of these ultraembedded/core_dbg_bridge is ranked #420,421 (28th percentile) for total stargazers, and #332,888 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #347/542.

ultraembedded/core_dbg_bridge is also tagged with popular topics, for these it's ranked: fpga (#367/479),  verilog (#220/284)

All Topics
axi4 fpga uart verilog

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0 commits on the default branch (master) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-11-24 @ 02:15am, id: 201753306 / R_kgDODAaC2g