chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

Date Created 2019-06-02 (5 years ago)

Commits 125 (last one about a year ago)

Stargazers 822 (0 this week)

Watchers 58 (0 this week)

Forks 221

License apache-2.0

Ranking

RepositoryStats indexes 585,332 repositories, of these chipsalliance/Cores-VeeR-EH1 is ranked #61,224 (90th percentile) for total stargazers, and #34,826 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #12/173.

chipsalliance/Cores-VeeR-EH1 is also tagged with popular topics, for these it's ranked: fpga (#46/478), risc-v (#39/263), riscv (#29/166)

Other Information

chipsalliance/Cores-VeeR-EH1 has 4 open pull requests on Github, 15 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 16 open issues and 83 closed issues.

All Topics

rtl axi4 fpga risc veer riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

6 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-21 @ 06:50pm, id: 189812971 / R_kgDOC1BQ6w