SystemRDL / PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Date Created 2020-11-11 (3 years ago)

Commits 172 (last one about a month ago)

Stargazers 47 (0 this week)

Watchers 15 (0 this week)

Forks 29

License gpl-3.0

Ranking

RepositoryStats indexes 534,551 repositories, of these SystemRDL/PeakRDL-regblock is ranked #445,607 (17th percentile) for total stargazers, and #142,015 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #83,158/103,470.

SystemRDL/PeakRDL-regblock is also tagged with popular topics, for these it's ranked: fpga (#380/435)

Other Information

SystemRDL/PeakRDL-regblock has 4 open pull requests on Github, 6 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 25 open issues and 72 closed issues.

There have been 21 releases, the latest one was published on 2024-04-01 (2 months ago) with the name 0.22.0.

Homepage URL: http://peakrdl-regblock.readthedocs.io

All Topics

csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler

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153 commits on the default branch (main) since jan '22

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The primary language is Python but there's also others...

updated: 2024-06-08 @ 01:38am, id: 311864195 / R_kgDOEpargw