SystemRDL / PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Date Created 2020-11-11 (4 years ago)

Commits 206 (last one 2 days ago)

Stargazers 60 (0 this week)

Watchers 16 (0 this week)

Forks 44

License gpl-3.0

Ranking

RepositoryStats indexes 638,560 repositories, of these SystemRDL/PeakRDL-regblock is ranked #437,637 (31st percentile) for total stargazers, and #134,766 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #85,402/130,935.

SystemRDL/PeakRDL-regblock is also tagged with popular topics, for these it's ranked: fpga (#388/525), systemverilog (#69/102)

Other Information

SystemRDL/PeakRDL-regblock has 2 open pull requests on Github, 7 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 14 open issues and 102 closed issues.

There have been 23 releases, the latest one was published on 2025-04-12 (2 days ago) with the name 1.0.0.

Homepage URL: http://peakrdl-regblock.readthedocs.io

All Topics

csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler

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Recent Commit History

187 commits on the default branch (main) since jan '22

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The primary language is Python but there's also others...

updated: 2025-04-13 @ 12:33am, id: 311864195 / R_kgDOEpargw