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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cpu asic fpga ariane risc-v rv64gc systemverilog-hdl

Created 2018-01-23

7,207 commits to master branch, last one 11 hours ago

263

738

other

VUnit is a unit testing framework for VHDL/SystemVerilog

asic fpga vhdl testbench verilog-hdl unit-testing verification systemverilog-hdl universal-verification-methodology

Created 2014-11-18

2,098 commits to master branch, last one 2 days ago

gpl-3.0

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler

Created 2020-11-11

172 commits to main branch, last one 6 months ago

apache-2.0

A SystemVerilog source file pickler.

rust picklers rickandmorty systemverilog-hdl

Created 2019-07-08

128 commits to master branch, last one 10 months ago