4 results found Sort:

openhwgroup
cva6 openhwgroup
706
2.3k
other
93
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cpu asic fpga ariane risc-v rv64gc systemverilog-hdl
Created 2018-01-23
7,263 commits to master branch, last one a day ago
VUnit
vunit VUnit
266
753
other
51
VUnit is a unit testing framework for VHDL/SystemVerilog
asic fpga vhdl testbench verilog-hdl unit-testing verification systemverilog-hdl universal-verification-methodology
Created 2014-11-18
2,109 commits to master branch, last one 8 days ago
SystemRDL
PeakRDL-regblock SystemRDL
43
55
gpl-3.0
15
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler
Created 2020-11-11
186 commits to main branch, last one a day ago
pulp-platform
morty pulp-platform
5
52
apache-2.0
5
A SystemVerilog source file pickler.
rust picklers rickandmorty systemverilog-hdl
Created 2019-07-08
128 commits to master branch, last one about a year ago