5 results found Sort:

openhwgroup
cva6 openhwgroup
743
2.4k
other
96
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cpu asic fpga ariane risc-v rv64gc systemverilog-hdl
Created 2018-01-23
7,351 commits to master branch, last one 2 days ago
VUnit
vunit VUnit
271
766
other
50
VUnit is a unit testing framework for VHDL/SystemVerilog
asic fpga vhdl testbench verilog-hdl unit-testing verification systemverilog-hdl universal-verification-methodology
Created 2014-11-18
2,126 commits to master branch, last one 27 days ago
SystemRDL
PeakRDL-regblock SystemRDL
44
59
gpl-3.0
15
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler
Created 2020-11-11
196 commits to main branch, last one 14 days ago
pulp-platform
morty pulp-platform
5
55
apache-2.0
5
A SystemVerilog source file pickler.
rust picklers rickandmorty systemverilog-hdl
Created 2019-07-08
128 commits to master branch, last one about a year ago
snbk001
100DaysofRTL snbk001
3
34
unknown
3
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge d...
hdl verilog makefile synthesis testbench rtl-design systemverilog systemverilog-hdl edge-detector-with-mealy systemverilog-simulation systemverilog-test-bench
Created 2022-09-28
152 commits to main branch, last one 2 years ago