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snbk001
100DaysofRTL snbk001
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100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge d...
hdl verilog makefile synthesis testbench rtl-design systemverilog systemverilog-hdl edge-detector-with-mealy systemverilog-simulation systemverilog-test-bench
Created 2022-09-28
152 commits to main branch, last one 2 years ago