snbk001 / 100DaysofRTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

Date Created 2022-09-28 (2 years ago)

Commits 152 (last one 2 years ago)

Stargazers 34 (0 this week)

Watchers 3 (0 this week)

Forks 3

License unknown

Ranking

RepositoryStats indexes 630,459 repositories, of these snbk001/100DaysofRTL is ranked #578,184 (8th percentile) for total stargazers, and #416,812 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #181/196.

snbk001/100DaysofRTL is also tagged with popular topics, for these it's ranked: verilog (#291/307)

All Topics

hdl verilog makefile synthesis testbench rtl-design systemverilog systemverilog-hdl edge-detector-with-mealy systemverilog-simulation systemverilog-test-bench

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Recent Commit History

152 commits on the default branch (main) since jan '22

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The primary language is SystemVerilog but there's also others...

updated: 2025-03-19 @ 02:31pm, id: 542641001 / R_kgDOIFgLaQ