WangXuan95 / BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Date Created 2022-02-20 (2 years ago)

Commits 19 (last one about a year ago)

Stargazers 495 (2 this week)

Watchers 10 (0 this week)

Forks 41

License gpl-3.0

Ranking

RepositoryStats indexes 565,279 repositories, of these WangXuan95/BSV_Tutorial_cn is ranked #89,412 (84th percentile) for total stargazers, and #203,735 for total watchers. Github reports the primary language for this repository as Bluespec, for repositories using this language it is ranked #1/7.

WangXuan95/BSV_Tutorial_cn is also tagged with popular topics, for these it's ranked: fpga (#71/462), verilog (#51/272)

Other Information

WangXuan95/BSV_Tutorial_cn has 1 open pull request on Github, 2 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 6 open issues and 19 closed issues.

Homepage URL: https://gitee.com/wangxuan95/BSV_Tutorial_cn

All Topics

bsv hdl fpga verilog bluespec bluespec-systemverilog hardware-description-language

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Github watchers over time, collection started in '23

Recent Commit History

19 commits on the default branch (main) since jan '22

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Languages

The primary language is Bluespec but there's also others...

updated: 2024-09-25 @ 10:54am, id: 461431074 / R_kgDOG4DhIg