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43

534

gpl-3.0

12

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

bsv hdl fpga verilog bluespec bluespec-systemverilog hardware-description-language

Created 2022-02-20

19 commits to main branch, last one about a year ago

46

162

mit

32

Connectal is a framework for software-driven hardware development.

fpga zynq verilog bluespec hardware

Created 2014-09-17

9,399 commits to master branch, last one about a year ago

24

144

mit

14

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

coq bluespec proof-assistant hardware-verification hardware-description-language

Created 2017-07-11

1,470 commits to rv32i branch, last one 2 months ago