suoglu / Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3

suoglu
suoglu
Date Created 2017-06-06 (7 years ago)
Commits 105 (last one about a year ago)
Stargazers 70 (0 this week)
Watchers 6 (0 this week)
Forks 14
License other
Ranking

RepositoryStats indexes 628,836 repositories, of these suoglu/Fixed-Floating-Point-Adder-Multiplier is ranked #389,776 (38th percentile) for total stargazers, and #288,850 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #323/613.

suoglu/Fixed-Floating-Point-Adder-Multiplier is also tagged with popular topics, for these it's ranked: fpga (#347/510),  hardware (#321/475),  verilog (#212/306)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

2 commits on the default branch (master) since jan '22

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Yearly Commits

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogTclTclPythonPython

updated: 2025-03-19 @ 04:02pm, id: 93567990 / R_kgDOBZO79g