suoglu / Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3

Date Created 2017-06-06 (7 years ago)

Commits 105 (last one about a year ago)

Stargazers 65 (0 this week)

Watchers 6 (0 this week)

Forks 14

License other

Ranking

RepositoryStats indexes 595,856 repositories, of these suoglu/Fixed-Floating-Point-Adder-Multiplier is ranked #393,883 (34th percentile) for total stargazers, and #300,666 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #322/563.

suoglu/Fixed-Floating-Point-Adder-Multiplier is also tagged with popular topics, for these it's ranked: fpga (#349/488), hardware (#319/451), verilog (#211/289)

All Topics

fpga adder vivado verilog binary16 hardware multiplier fixed-point floating-point

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2 commits on the default branch (master) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-12-12 @ 11:32pm, id: 93567990 / R_kgDOBZO79g